Design of a Low Density Parity Check Iterative Decoder

A Low Density Parity Check iterative decoder is implemented in 0.13 μm CMOS technology with 6 metal layers. Using a 1023 x 32 parity-check matrix, this code has at least an order of magnitude less computational requirement than traditional error correcting methods that provide similar bit-error rate performance. Power and throughput optimization is achieved through exploitation of massive amount of parallelism in the decoding algorithm, while maintaining a manageable core area. The implementation and design flow of the LDPC decoder using computer-aided design tools are discussed. The LDPC decoder design occupies an area of 1.5mm x 1.5mm.